1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a device isolation layer of a semiconductor device. Herein, by partially masking a center region of a wafer, when forming a trench isolation layer by using a high density plasma (HDP) process, and by etching edge regions of the wafer, the thickness of the center region and the edge regions of the wafer can become uniform.
2. Discussion of the Related Art
In a semiconductor, a plurality of cells formed in unit devices, such as transistors, capacitors, and so on, are integrated on a limited surface depending on the capacity of the semiconductor device. Due to the individual operation characteristics of each cell, the cells require to be electrically isolated.
Therefore, as a method for electrically isolating each of the cells, LOCal Oxidation of Silicon (LOCOS) and Shallow Trench Isolation (STI) are well known. LOCOS recesses a silicon substrate and develops a field oxidation layer. STI etches a wafer in a vertical direction and fills the trenches formed in the wafer with an isolation material.
STI uses dry-etching methods, such as Reactive Ion Etching (RIE) or plasma etching, to form narrow and deep trenches. Thereafter, the trenches are filled with isolation layers. More specifically, a trench is formed in a silicon wafer, which is then filled with an isolation layer, thereby resolving the problems related to birds beak. In addition, the trench filled with the isolation layer planarizes the surface. Therefore, this method is advantageous in forming fine devices, since the area occupied by the device isolation area is reduced.
As described above, STI is advantageous in ensuring a larger active area for the device. In addition, STI have more enhanced characteristics in the aspect of leakage current caused by connection as compared to LOCOS.
FIG. 1A to FIG. 1D illustrate cross-sectional views showing a process of a related art method for forming a device isolation layer of a semiconductor device.
Referring to FIG. 1A, a pad oxidation layer 13 is formed on a silicon substrate 11, on which a trench for isolating devices is to be formed. Then, a nitride layer 15 is deposited on the pad oxidation layer 13. A photoresist layer 17 is formed by coating a photoresist material, which will be used as an etching mask. The photoresist layer 17 is then patterned, so as to form a photoresist pattern that exposes the area that is to be etched.
Referring to FIG. 1B, the photoresist layer 17 is used as a mask to selectively dry-etch the nitride layer 15 and the pad oxidation layer 13 until the silicon substrate 11 is exposed. Then, the exposed portion of the silicon substrate 11 is dry-etched to a predetermined thickness, so as to form a trench (T).
As shown in FIG. 1C, the photoresist layer 17 is removed and the structure is washed. Subsequently, an STI liner oxidation process is performed. In other words, the surface of the trench (T) is developed by a heating process, thereby forming a liner oxidation layer 19.
Thereafter, a trench filling material is deposited on the entire surface of the structure including the trench (T), so as to form a trench isolation layer 21. The trench isolation layer 21 has usually been deposited by using an Atmospheric Pressure Chemical Vapor Deposition (APCVD) method or a Sub Atmospheric Pressure Chemical Vapor Deposition (SAPCVD) method. Recently, however, as devices have become highly integrated, a high density plasma (HDP) method is being used in order to obtain an excellent gap filling effect.
Referring to FIG. 1D, a Chemical Mechanical Polishing (CMP) process is performed to remove the trench isolation layer 21 remaining on a portion above the nitride layer 15. Thus, the trench isolation layer 21 only exists in the trench (T) area, i.e., the inactive area. After a plurality of processes, such as an ion injection process, and so on, a pre-washing process is performed, so as to develop a gate oxidation layer.
The above-described related method for forming the device isolation layer of the semiconductor device uses the HDP process when forming the trench isolation layer. However, due to the deposition mechanism in the related art method, as deposition and etching processes are performed simultaneously, the HDP process may cause non-uniformity in that the edge regions of the wafer are formed to be thicker than the center region of the wafer, as shown in FIG. 1C. Then, even after performing a planarization process, the edge regions of the wafer may still remain thicker than the center region of the wafer, as shown in FIG. 1D. The deposition profile of the trench isolation layer shown throughout the entire wafer is shown in the graph of FIG. 2.
Therefore, in a later process, due to a step difference in the active area, where the transistor or capacitor is formed, and the field area, which is the device isolation area, a difference in thickness may occur between the center region of the wafer and the edge regions of the wafer, thereby causing a difference in characteristics among the devices.